1. Field of the Invention
The present invention relates to a test system for various circuits. More particularly, the present invention relates to a test system, for various circuits, suitable for testing an integrated circuit memory device or the like.
2. Description of the Related Art
In the field of testing a memory device, a stored program method is normally adopted for a conventional test system that is a test system for circuits. Herein, for a better understanding of problems underlying conventional test systems for circuits, the configuration of a conventional test system, for circuits, adopting the stored program method and the operations thereof will be described in conjunction with FIG. 1, FIG. 2A and FIG. 2B that will be described in “Brief Description of the Drawings” later.
An explanatory diagram concerning the conventional stored program method is illustrated in FIG. 1. Referring to FIG. 1, there are shown a tester 1, a tester body 2, an instruction memory 3, a test pattern processor 4, a jig portion 5 (or interface unit) through which an object to be tested and the tester are connected to each other, a memory device or memory module 6 that is an object to be tested, a test assembly language 7, an assembler 8, and a test program 9. The jig portion 5 consists of an object-to-be-tested connector interface or an object-to-be-tested interface circuit.
In the thus configured system, the test assembly language 7 is used to describe an algorithm for producing a test pattern. The assembler 8 assembles the algorithm, thus producing the test program 9. The test program 9 is stored in the instruction memory 3 included in the tester 1. The pattern processor 4 included in the tester reads out the stored test program from the instruction memory 3, and interprets what instruction is indicated by the read numerical values. Thus, the test pattern is produced.
A test signal having the produced test pattern is applied to the object to be tested 6 through the interface unit 5, in accordance with an access protocol defined exclusively for the object to be tested 6. Thereafter, the next instruction is read out from the instruction memory 3, and a series of operations, that is, interpretations and executions, are carried out repeatedly.
The above-mentioned sequence will be itemized in the form of the following steps.
(1) Down-loading the test program into the instruction memory
(2) Starting a test
(3) Reading out numerical values from the instruction memory
(4) Interpreting what instruction, written in a machine language, is indicated by the numerical values
(5) Executing the instruction
(6) Transmitting an execution pattern to the interface circuit
(7) Applying a test signal having the above pattern to the object to be tested 6 (memory device or memory module) through the interface circuit
(8) Reading the next instruction from the instruction memory, and repeating the above steps (4) to (8)
(9) Completing the test
In the conventional stored program method, when the tester 1 executes one instruction described in a test program for the object to be tested, the steps of reading out the instruction memory 3, interpreting what instruction is indicated by the numerical value, and executing the instruction (usually referred to as a fetch cycle) must be carried out without fail. This situation remarkably affects the operating speed of a test system.
Moreover, a conventional test circuit system may adopt a method, of testing an object to be tested, by transferring a test pattern to the object to be tested by using a field programmable gate array (usually abbreviated to FPGA; a registered trademark granted to Zilinks Corporation). According to this method, program data is transferred to the FPGA so as to generate a predetermined test pattern that is used to test a circuit to be tested.
Whatever method may be adopted, a hardware architecture of a conventional system is fixed and, also, conditions for assignment of test signal components to pins of input and output ports are fixed. The arrangement of address lines and data lines varies depending on an object to be tested, while it is determined what signals are transferred through respectively corresponding pins in a tester. Therefore, the line connection between an object to be tested and an interface unit (jig portion) 5 is complicated. There is a disadvantage that the signal transmission lines cannot cope with high speed signals.
First and second examples of a pin configuration in a conventional test system, is illustrated in FIG. 2A and FIG. 2B. Herein, two examples are shown in FIG. 2A and FIG. 2B. In FIG. 2A and FIG. 2B, there is shown a test pattern processor 4 whose pin configuration is fixed. More specifically, address pins (AD0 to AD7) and data pins (DO0 to DO7) are juxtaposed in that order from left to right. The test pattern processor 4 and the object to be tested are connected to each other, through a jig portion 5. The pin configuration of the object to be tested 6 varies depending on the type of the object to be tested. In the first example shown in FIG. 2A, the data pins DO0 to DO3, address pins AD0 to AD7, and data pins DO4 to DO7 are juxtaposed in that order from left to right.
It is therefore impossible to directly connect the test pattern processor 4 to the object to be tested 6, by using a plurality of lines for connecting the test pattern processor 4 to the object to be tested 6 from the lower part to the upper part, without making these lines intersect with each other. The jig 5 is therefore used to adjust a difference concerning the pin configuration between the test pattern processor 4 and the object to be tested 6. The lines therefore intersect with each other on the jig portion 5.
On the other hand, in the second example shown in FIG. 2B, the pin configuration of the object to be tested 6 is more complicated than that in the first example shown in FIG. 2A. The pins DO0 to DO3, AD0 to AD3, DO4 to DO7, and AD4 to AD7 are juxtaposed in that order from left to right. The number of intersections of lines on the jig portion 5 is therefore larger than that shown in FIG. 2A.
In recent years, memory devices (modules) have come to require a complicated access protocol and operate at remarkably high speeds. A tester is therefore required to operate at higher speeds and cope with various complicated access protocols. Therefore, various attempts have been made to cope with these disadvantages. More specifically, a dedicated LSI has been developed in order to resolve a delay in the operation caused by a fetch cycle, or an interface has been incorporated into a tester in order to cope with various kinds of objects to be tested, or the interface, per se, has been included in a jig portion.
Not only a test system for testing a memory device but also the other various test systems have configurations in which the architecture of each tester is fixed. Each of the test systems cannot provide capabilities other than those defined by the determined architecture of the tester. For this reason, each of the test systems is designed to provide various capabilities from the beginning and are therefore complicated, relatively large in size, and expensive.